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// Copyright (c) 2011-present, Facebook, Inc. All rights reserved.
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// This source code is licensed under both the GPLv2 (found in the
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// COPYING file in the root directory) and Apache 2.0 License
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// (found in the LICENSE.Apache file in the root directory).
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Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
5 years ago
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#ifndef ROCKSDB_LITE
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#ifndef GFLAGS
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#include <cstdio>
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int main() {
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fprintf(stderr,
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"Please install gflags to run block_cache_trace_analyzer_test\n");
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return 1;
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}
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#else
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#include <fstream>
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#include <iostream>
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#include <map>
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#include <vector>
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#include "rocksdb/env.h"
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#include "rocksdb/status.h"
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#include "rocksdb/trace_reader_writer.h"
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#include "test_util/testharness.h"
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#include "test_util/testutil.h"
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#include "tools/block_cache_trace_analyzer.h"
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#include "trace_replay/block_cache_tracer.h"
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namespace rocksdb {
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namespace {
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const uint64_t kBlockSize = 1024;
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const std::string kBlockKeyPrefix = "test-block-";
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const uint32_t kCFId = 0;
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const uint32_t kLevel = 1;
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const uint64_t kSSTStoringEvenKeys = 100;
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const uint64_t kSSTStoringOddKeys = 101;
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const std::string kRefKeyPrefix = "test-get-";
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const uint64_t kNumKeysInBlock = 1024;
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Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
5 years ago
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const int kMaxArgCount = 100;
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const size_t kArgBufferSize = 100000;
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} // namespace
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class BlockCacheTracerTest : public testing::Test {
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public:
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BlockCacheTracerTest() {
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test_path_ = test::PerThreadDBPath("block_cache_tracer_test");
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env_ = rocksdb::Env::Default();
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EXPECT_OK(env_->CreateDir(test_path_));
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trace_file_path_ = test_path_ + "/block_cache_trace";
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Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
5 years ago
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block_cache_sim_config_path_ = test_path_ + "/block_cache_sim_config";
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timeline_labels_ =
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"block,all,cf,sst,level,bt,caller,cf_sst,cf_level,cf_bt,cf_caller";
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reuse_distance_labels_ =
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"block,all,cf,sst,level,bt,caller,cf_sst,cf_level,cf_bt,cf_caller";
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reuse_distance_buckets_ = "1,1K,1M,1G";
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reuse_interval_labels_ = "block,all,cf,sst,level,bt,cf_sst,cf_level,cf_bt";
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reuse_interval_buckets_ = "1,10,100,1000";
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}
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~BlockCacheTracerTest() override {
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if (getenv("KEEP_DB")) {
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printf("The trace file is still at %s\n", trace_file_path_.c_str());
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return;
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}
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EXPECT_OK(env_->DeleteFile(trace_file_path_));
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EXPECT_OK(env_->DeleteDir(test_path_));
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}
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TableReaderCaller GetCaller(uint32_t key_id) {
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uint32_t n = key_id % 5;
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switch (n) {
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case 0:
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return TableReaderCaller::kPrefetch;
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case 1:
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return TableReaderCaller::kCompaction;
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case 2:
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return TableReaderCaller::kUserGet;
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case 3:
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return TableReaderCaller::kUserMultiGet;
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case 4:
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return TableReaderCaller::kUserIterator;
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}
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// This cannot happend.
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assert(false);
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return TableReaderCaller::kMaxBlockCacheLookupCaller;
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}
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void WriteBlockAccess(BlockCacheTraceWriter* writer, uint32_t from_key_id,
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TraceType block_type, uint32_t nblocks) {
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assert(writer);
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for (uint32_t i = 0; i < nblocks; i++) {
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uint32_t key_id = from_key_id + i;
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uint64_t timestamp = (key_id + 1) * kMicrosInSecond;
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BlockCacheTraceRecord record;
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record.block_type = block_type;
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record.block_size = kBlockSize + key_id;
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record.block_key = kBlockKeyPrefix + std::to_string(key_id);
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record.access_timestamp = timestamp;
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record.cf_id = kCFId;
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record.cf_name = kDefaultColumnFamilyName;
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record.caller = GetCaller(key_id);
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record.level = kLevel;
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if (key_id % 2 == 0) {
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record.sst_fd_number = kSSTStoringEvenKeys;
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} else {
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record.sst_fd_number = kSSTStoringOddKeys;
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}
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record.is_cache_hit = Boolean::kFalse;
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record.no_insert = Boolean::kFalse;
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// Provide these fields for all block types.
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// The writer should only write these fields for data blocks and the
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// caller is either GET or MGET.
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record.referenced_key = kRefKeyPrefix + std::to_string(key_id);
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record.referenced_key_exist_in_block = Boolean::kTrue;
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record.num_keys_in_block = kNumKeysInBlock;
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ASSERT_OK(writer->WriteBlockAccess(
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record, record.block_key, record.cf_name, record.referenced_key));
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}
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}
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void AssertBlockAccessInfo(
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uint32_t key_id, TraceType type,
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const std::map<std::string, BlockAccessInfo>& block_access_info_map) {
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auto key_id_str = kBlockKeyPrefix + std::to_string(key_id);
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ASSERT_TRUE(block_access_info_map.find(key_id_str) !=
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block_access_info_map.end());
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auto& block_access_info = block_access_info_map.find(key_id_str)->second;
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ASSERT_EQ(1, block_access_info.num_accesses);
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ASSERT_EQ(kBlockSize + key_id, block_access_info.block_size);
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ASSERT_GT(block_access_info.first_access_time, 0);
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ASSERT_GT(block_access_info.last_access_time, 0);
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ASSERT_EQ(1, block_access_info.caller_num_access_map.size());
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TableReaderCaller expected_caller = GetCaller(key_id);
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ASSERT_TRUE(block_access_info.caller_num_access_map.find(expected_caller) !=
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block_access_info.caller_num_access_map.end());
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ASSERT_EQ(
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1,
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block_access_info.caller_num_access_map.find(expected_caller)->second);
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if ((expected_caller == TableReaderCaller::kUserGet ||
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expected_caller == TableReaderCaller::kUserMultiGet) &&
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type == TraceType::kBlockTraceDataBlock) {
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ASSERT_EQ(kNumKeysInBlock, block_access_info.num_keys);
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ASSERT_EQ(1, block_access_info.key_num_access_map.size());
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ASSERT_EQ(0, block_access_info.non_exist_key_num_access_map.size());
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ASSERT_EQ(1, block_access_info.num_referenced_key_exist_in_block);
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}
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}
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Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
5 years ago
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void RunBlockCacheTraceAnalyzer() {
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std::vector<std::string> params = {
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"./block_cache_trace_analyzer",
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"-block_cache_trace_path=" + trace_file_path_,
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"-block_cache_sim_config_path=" + block_cache_sim_config_path_,
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"-block_cache_analysis_result_dir=" + test_path_,
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Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
5 years ago
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"-print_block_size_stats",
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"-print_access_count_stats",
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"-print_data_block_access_count_stats",
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"-cache_sim_warmup_seconds=0",
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"-timeline_labels=" + timeline_labels_,
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"-reuse_distance_labels=" + reuse_distance_labels_,
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"-reuse_distance_buckets=" + reuse_distance_buckets_,
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"-reuse_interval_labels=" + reuse_interval_labels_,
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"-reuse_interval_buckets=" + reuse_interval_buckets_,
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};
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Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
5 years ago
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char arg_buffer[kArgBufferSize];
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char* argv[kMaxArgCount];
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int argc = 0;
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int cursor = 0;
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for (const auto& arg : params) {
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ASSERT_LE(cursor + arg.size() + 1, kArgBufferSize);
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ASSERT_LE(argc + 1, kMaxArgCount);
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snprintf(arg_buffer + cursor, arg.size() + 1, "%s", arg.c_str());
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argv[argc++] = arg_buffer + cursor;
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cursor += static_cast<int>(arg.size()) + 1;
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}
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ASSERT_EQ(0, rocksdb::block_cache_trace_analyzer_tool(argc, argv));
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}
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Env* env_;
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EnvOptions env_options_;
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Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
5 years ago
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std::string block_cache_sim_config_path_;
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std::string trace_file_path_;
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std::string test_path_;
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std::string timeline_labels_;
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std::string reuse_distance_labels_;
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std::string reuse_distance_buckets_;
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std::string reuse_interval_labels_;
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std::string reuse_interval_buckets_;
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};
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Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
5 years ago
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TEST_F(BlockCacheTracerTest, BlockCacheAnalyzer) {
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{
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// Generate a trace file.
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TraceOptions trace_opt;
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std::unique_ptr<TraceWriter> trace_writer;
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ASSERT_OK(NewFileTraceWriter(env_, env_options_, trace_file_path_,
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&trace_writer));
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BlockCacheTraceWriter writer(env_, trace_opt, std::move(trace_writer));
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ASSERT_OK(writer.WriteHeader());
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WriteBlockAccess(&writer, 0, TraceType::kBlockTraceDataBlock, 50);
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ASSERT_OK(env_->FileExists(trace_file_path_));
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}
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{
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// Generate a cache sim config.
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std::string config = "lru,1,0,1K,1M,1G";
|
Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
5 years ago
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std::ofstream out(block_cache_sim_config_path_);
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ASSERT_TRUE(out.is_open());
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out << config << std::endl;
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out.close();
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}
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RunBlockCacheTraceAnalyzer();
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{
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// Validate the cache miss ratios.
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const std::vector<uint64_t> expected_capacities{1024, 1024 * 1024,
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1024 * 1024 * 1024};
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const std::string mrc_path = test_path_ + "/mrc";
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std::ifstream infile(mrc_path);
|
Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
5 years ago
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uint32_t config_index = 0;
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std::string line;
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// Read header.
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ASSERT_TRUE(getline(infile, line));
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while (getline(infile, line)) {
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std::stringstream ss(line);
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std::vector<std::string> result_strs;
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while (ss.good()) {
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std::string substr;
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getline(ss, substr, ',');
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result_strs.push_back(substr);
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}
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ASSERT_EQ(6, result_strs.size());
|
Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
5 years ago
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ASSERT_LT(config_index, expected_capacities.size());
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ASSERT_EQ("lru", result_strs[0]); // cache_name
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ASSERT_EQ("1", result_strs[1]); // num_shard_bits
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ASSERT_EQ("0", result_strs[2]); // ghost_cache_capacity
|
Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
5 years ago
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ASSERT_EQ(std::to_string(expected_capacities[config_index]),
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result_strs[3]); // cache_capacity
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ASSERT_EQ("100.0000", result_strs[4]); // miss_ratio
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ASSERT_EQ("50", result_strs[5]); // number of accesses.
|
Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
5 years ago
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config_index++;
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}
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ASSERT_EQ(expected_capacities.size(), config_index);
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infile.close();
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ASSERT_OK(env_->DeleteFile(mrc_path));
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}
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{
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// Validate the timeline csv files.
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const uint32_t expected_num_lines = 50;
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std::stringstream ss(timeline_labels_);
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while (ss.good()) {
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std::string l;
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ASSERT_TRUE(getline(ss, l, ','));
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const std::string timeline_file =
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test_path_ + "/" + l + "_access_timeline";
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std::ifstream infile(timeline_file);
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std::string line;
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uint32_t nlines = 0;
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ASSERT_TRUE(getline(infile, line));
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uint64_t expected_time = 1;
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while (getline(infile, line)) {
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std::stringstream ss_naccess(line);
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uint32_t naccesses = 0;
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std::string substr;
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uint32_t time = 0;
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while (ss_naccess.good()) {
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ASSERT_TRUE(getline(ss_naccess, substr, ','));
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if (time == 0) {
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time = ParseUint32(substr);
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continue;
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}
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naccesses += ParseUint32(substr);
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}
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nlines++;
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ASSERT_EQ(1, naccesses);
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ASSERT_EQ(expected_time, time);
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expected_time += 1;
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}
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ASSERT_EQ(expected_num_lines, nlines);
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ASSERT_OK(env_->DeleteFile(timeline_file));
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}
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}
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{
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// Validate the reuse_interval and reuse_distance csv files.
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std::map<std::string, std::string> test_reuse_csv_files;
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test_reuse_csv_files["_reuse_interval"] = reuse_interval_labels_;
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test_reuse_csv_files["_reuse_distance"] = reuse_distance_labels_;
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for (auto const& test : test_reuse_csv_files) {
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const std::string& file_suffix = test.first;
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const std::string& labels = test.second;
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const uint32_t expected_num_rows = 10;
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const uint32_t expected_num_rows_absolute_values = 5;
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const uint32_t expected_reused_blocks = 0;
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std::stringstream ss(labels);
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while (ss.good()) {
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std::string l;
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ASSERT_TRUE(getline(ss, l, ','));
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const std::string reuse_csv_file = test_path_ + "/" + l + file_suffix;
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std::ifstream infile(reuse_csv_file);
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std::string line;
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ASSERT_TRUE(getline(infile, line));
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uint32_t nblocks = 0;
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double npercentage = 0;
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uint32_t nrows = 0;
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while (getline(infile, line)) {
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std::stringstream ss_naccess(line);
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bool label_read = false;
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nrows++;
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while (ss_naccess.good()) {
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std::string substr;
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ASSERT_TRUE(getline(ss_naccess, substr, ','));
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|
if (!label_read) {
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|
label_read = true;
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|
continue;
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|
|
|
}
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|
|
if (nrows < expected_num_rows_absolute_values) {
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|
|
nblocks += ParseUint32(substr);
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|
|
|
} else {
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|
|
|
npercentage += ParseDouble(substr);
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|
|
|
}
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|
|
|
}
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|
|
|
}
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|
ASSERT_EQ(expected_num_rows, nrows);
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ASSERT_EQ(expected_reused_blocks, nblocks);
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ASSERT_LT(npercentage, 0);
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ASSERT_OK(env_->DeleteFile(reuse_csv_file));
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|
|
|
}
|
|
|
|
}
|
Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
5 years ago
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|
|
}
|
|
|
|
ASSERT_OK(env_->DeleteFile(block_cache_sim_config_path_));
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|
|
|
}
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|
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|
TEST_F(BlockCacheTracerTest, MixedBlocks) {
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{
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|
// Generate a trace file containing a mix of blocks.
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// It contains two SST files with 25 blocks of odd numbered block_key in
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// kSSTStoringOddKeys and 25 blocks of even numbered blocks_key in
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// kSSTStoringEvenKeys.
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TraceOptions trace_opt;
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std::unique_ptr<TraceWriter> trace_writer;
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ASSERT_OK(NewFileTraceWriter(env_, env_options_, trace_file_path_,
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|
|
&trace_writer));
|
|
|
|
BlockCacheTraceWriter writer(env_, trace_opt, std::move(trace_writer));
|
|
|
|
ASSERT_OK(writer.WriteHeader());
|
|
|
|
// Write blocks of different types.
|
|
|
|
WriteBlockAccess(&writer, 0, TraceType::kBlockTraceUncompressionDictBlock,
|
|
|
|
10);
|
|
|
|
WriteBlockAccess(&writer, 10, TraceType::kBlockTraceDataBlock, 10);
|
|
|
|
WriteBlockAccess(&writer, 20, TraceType::kBlockTraceFilterBlock, 10);
|
|
|
|
WriteBlockAccess(&writer, 30, TraceType::kBlockTraceIndexBlock, 10);
|
|
|
|
WriteBlockAccess(&writer, 40, TraceType::kBlockTraceRangeDeletionBlock, 10);
|
|
|
|
ASSERT_OK(env_->FileExists(trace_file_path_));
|
|
|
|
}
|
|
|
|
|
|
|
|
{
|
|
|
|
// Verify trace file is generated correctly.
|
|
|
|
std::unique_ptr<TraceReader> trace_reader;
|
|
|
|
ASSERT_OK(NewFileTraceReader(env_, env_options_, trace_file_path_,
|
|
|
|
&trace_reader));
|
|
|
|
BlockCacheTraceReader reader(std::move(trace_reader));
|
|
|
|
BlockCacheTraceHeader header;
|
|
|
|
ASSERT_OK(reader.ReadHeader(&header));
|
|
|
|
ASSERT_EQ(kMajorVersion, header.rocksdb_major_version);
|
|
|
|
ASSERT_EQ(kMinorVersion, header.rocksdb_minor_version);
|
|
|
|
// Read blocks.
|
Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
5 years ago
|
|
|
BlockCacheTraceAnalyzer analyzer(trace_file_path_,
|
|
|
|
/*output_miss_ratio_curve_path=*/"",
|
|
|
|
/*simulator=*/nullptr);
|
|
|
|
// The analyzer ends when it detects an incomplete access record.
|
|
|
|
ASSERT_EQ(Status::Incomplete(""), analyzer.Analyze());
|
|
|
|
const uint64_t expected_num_cfs = 1;
|
|
|
|
std::vector<uint64_t> expected_fds{kSSTStoringOddKeys, kSSTStoringEvenKeys};
|
|
|
|
const std::vector<TraceType> expected_types{
|
|
|
|
TraceType::kBlockTraceUncompressionDictBlock,
|
|
|
|
TraceType::kBlockTraceDataBlock, TraceType::kBlockTraceFilterBlock,
|
|
|
|
TraceType::kBlockTraceIndexBlock,
|
|
|
|
TraceType::kBlockTraceRangeDeletionBlock};
|
|
|
|
const uint64_t expected_num_keys_per_type = 5;
|
|
|
|
|
|
|
|
auto& stats = analyzer.TEST_cf_aggregates_map();
|
|
|
|
ASSERT_EQ(expected_num_cfs, stats.size());
|
|
|
|
ASSERT_TRUE(stats.find(kDefaultColumnFamilyName) != stats.end());
|
|
|
|
auto& cf_stats = stats.find(kDefaultColumnFamilyName)->second;
|
|
|
|
ASSERT_EQ(expected_fds.size(), cf_stats.fd_aggregates_map.size());
|
|
|
|
for (auto fd_id : expected_fds) {
|
|
|
|
ASSERT_TRUE(cf_stats.fd_aggregates_map.find(fd_id) !=
|
|
|
|
cf_stats.fd_aggregates_map.end());
|
|
|
|
ASSERT_EQ(kLevel, cf_stats.fd_aggregates_map.find(fd_id)->second.level);
|
|
|
|
auto& block_type_aggregates_map = cf_stats.fd_aggregates_map.find(fd_id)
|
|
|
|
->second.block_type_aggregates_map;
|
|
|
|
ASSERT_EQ(expected_types.size(), block_type_aggregates_map.size());
|
|
|
|
uint32_t key_id = 0;
|
|
|
|
for (auto type : expected_types) {
|
|
|
|
ASSERT_TRUE(block_type_aggregates_map.find(type) !=
|
|
|
|
block_type_aggregates_map.end());
|
|
|
|
auto& block_access_info_map =
|
|
|
|
block_type_aggregates_map.find(type)->second.block_access_info_map;
|
|
|
|
// Each block type has 5 blocks.
|
|
|
|
ASSERT_EQ(expected_num_keys_per_type, block_access_info_map.size());
|
|
|
|
for (uint32_t i = 0; i < 10; i++) {
|
|
|
|
// Verify that odd numbered blocks are stored in kSSTStoringOddKeys
|
|
|
|
// and even numbered blocks are stored in kSSTStoringEvenKeys.
|
|
|
|
auto key_id_str = kBlockKeyPrefix + std::to_string(key_id);
|
|
|
|
if (fd_id == kSSTStoringOddKeys) {
|
|
|
|
if (key_id % 2 == 1) {
|
|
|
|
AssertBlockAccessInfo(key_id, type, block_access_info_map);
|
|
|
|
} else {
|
|
|
|
ASSERT_TRUE(block_access_info_map.find(key_id_str) ==
|
|
|
|
block_access_info_map.end());
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (key_id % 2 == 1) {
|
|
|
|
ASSERT_TRUE(block_access_info_map.find(key_id_str) ==
|
|
|
|
block_access_info_map.end());
|
|
|
|
} else {
|
|
|
|
AssertBlockAccessInfo(key_id, type, block_access_info_map);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
key_id++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
} // namespace rocksdb
|
|
|
|
|
|
|
|
int main(int argc, char** argv) {
|
|
|
|
::testing::InitGoogleTest(&argc, argv);
|
|
|
|
return RUN_ALL_TESTS();
|
|
|
|
}
|
Support computing miss ratio curves using sim_cache. (#5449)
Summary:
This PR adds a BlockCacheTraceSimulator that reports the miss ratios given different cache configurations. A cache configuration contains "cache_name,num_shard_bits,cache_capacities". For example, "lru, 1, 1K, 2K, 4M, 4G".
When we replay the trace, we also perform lookups and inserts on the simulated caches.
In the end, it reports the miss ratio for each tuple <cache_name, num_shard_bits, cache_capacity> in a output file.
This PR also adds a main source block_cache_trace_analyzer so that we can run the analyzer in command line.
Pull Request resolved: https://github.com/facebook/rocksdb/pull/5449
Test Plan:
Added tests for block_cache_trace_analyzer.
COMPILE_WITH_ASAN=1 make check -j32.
Differential Revision: D15797073
Pulled By: HaoyuHuang
fbshipit-source-id: aef0c5c2e7938f3e8b6a10d4a6a50e6928ecf408
5 years ago
|
|
|
#endif // GFLAG
|
|
|
|
#else
|
|
|
|
#include <stdio.h>
|
|
|
|
int main(int /*argc*/, char** /*argv*/) {
|
|
|
|
fprintf(stderr,
|
|
|
|
"block_cache_trace_analyzer_test is not supported in ROCKSDB_LITE\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif // ROCKSDB_LITE
|