Cache simulator: Refactor the cache simulator so that we can add alternative policies easily (#5517)
Summary: This PR creates cache_simulator.h file. It contains a CacheSimulator that runs against a block cache trace record. We can add alternative cache simulators derived from CacheSimulator later. For example, this PR adds a PrioritizedCacheSimulator that inserts filter/index/uncompressed dictionary blocks with high priority. Pull Request resolved: https://github.com/facebook/rocksdb/pull/5517 Test Plan: make clean && COMPILE_WITH_ASAN=1 make check -j32 Differential Revision: D16043689 Pulled By: HaoyuHuang fbshipit-source-id: 65f28ed52b866ffb0e6eceffd7f9ca7c45bb680dmain
haoyuhuang
6 years ago
committed by
Facebook Github Bot
parent
3886dddc3b
commit
9f0bd56889
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// Copyright (c) 2011-present, Facebook, Inc. All rights reserved.
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// This source code is licensed under both the GPLv2 (found in the
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// COPYING file in the root directory) and Apache 2.0 License
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// (found in the LICENSE.Apache file in the root directory).
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#include "utilities/simulator_cache/cache_simulator.h" |
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namespace rocksdb { |
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CacheSimulator::CacheSimulator(std::shared_ptr<SimCache> sim_cache) |
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: sim_cache_(sim_cache) {} |
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void CacheSimulator::Access(const BlockCacheTraceRecord& access) { |
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auto handle = sim_cache_->Lookup(access.block_key); |
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if (handle == nullptr && !access.no_insert) { |
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sim_cache_->Insert(access.block_key, /*value=*/nullptr, access.block_size, |
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/*deleter=*/nullptr, /*handle=*/nullptr); |
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} |
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} |
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void PrioritizedCacheSimulator::Access(const BlockCacheTraceRecord& access) { |
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auto handle = sim_cache_->Lookup(access.block_key); |
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if (handle == nullptr && !access.no_insert) { |
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Cache::Priority priority = Cache::Priority::LOW; |
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if (access.block_type == TraceType::kBlockTraceFilterBlock || |
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access.block_type == TraceType::kBlockTraceIndexBlock || |
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access.block_type == TraceType::kBlockTraceUncompressionDictBlock) { |
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priority = Cache::Priority::HIGH; |
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} |
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sim_cache_->Insert(access.block_key, /*value=*/nullptr, access.block_size, |
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/*deleter=*/nullptr, /*handle=*/nullptr, priority); |
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} |
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} |
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double CacheSimulator::miss_ratio() { |
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uint64_t hits = sim_cache_->get_hit_counter(); |
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uint64_t misses = sim_cache_->get_miss_counter(); |
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uint64_t total_accesses = hits + misses; |
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return static_cast<double>(misses * 100.0 / total_accesses); |
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} |
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uint64_t CacheSimulator::total_accesses() { |
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return sim_cache_->get_hit_counter() + sim_cache_->get_miss_counter(); |
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} |
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BlockCacheTraceSimulator::BlockCacheTraceSimulator( |
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uint64_t warmup_seconds, uint32_t downsample_ratio, |
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const std::vector<CacheConfiguration>& cache_configurations) |
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: warmup_seconds_(warmup_seconds), |
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downsample_ratio_(downsample_ratio), |
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cache_configurations_(cache_configurations) {} |
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Status BlockCacheTraceSimulator::InitializeCaches() { |
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for (auto const& config : cache_configurations_) { |
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for (auto cache_capacity : config.cache_capacities) { |
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// Scale down the cache capacity since the trace contains accesses on
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// 1/'downsample_ratio' blocks.
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uint64_t simulate_cache_capacity = cache_capacity / downsample_ratio_; |
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std::shared_ptr<CacheSimulator> sim_cache; |
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if (config.cache_name == "lru") { |
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sim_cache = std::make_shared<CacheSimulator>(NewSimCache( |
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NewLRUCache(simulate_cache_capacity, config.num_shard_bits, |
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/*strict_capacity_limit=*/false, |
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/*high_pri_pool_ratio=*/0), |
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/*real_cache=*/nullptr, config.num_shard_bits)); |
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} else if (config.cache_name == "lru_priority") { |
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sim_cache = std::make_shared<PrioritizedCacheSimulator>(NewSimCache( |
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NewLRUCache(simulate_cache_capacity, config.num_shard_bits, |
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/*strict_capacity_limit=*/false, |
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/*high_pri_pool_ratio=*/0.5), |
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/*real_cache=*/nullptr, config.num_shard_bits)); |
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} else { |
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// Not supported.
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return Status::InvalidArgument("Unknown cache name " + |
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config.cache_name); |
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} |
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sim_caches_[config].push_back(sim_cache); |
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} |
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} |
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return Status::OK(); |
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} |
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void BlockCacheTraceSimulator::Access(const BlockCacheTraceRecord& access) { |
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if (trace_start_time_ == 0) { |
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trace_start_time_ = access.access_timestamp; |
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} |
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// access.access_timestamp is in microseconds.
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if (!warmup_complete_ && |
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trace_start_time_ + warmup_seconds_ * kMicrosInSecond <= |
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access.access_timestamp) { |
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for (auto& config_caches : sim_caches_) { |
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for (auto& sim_cache : config_caches.second) { |
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sim_cache->reset_counter(); |
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} |
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} |
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warmup_complete_ = true; |
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} |
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for (auto& config_caches : sim_caches_) { |
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for (auto& sim_cache : config_caches.second) { |
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sim_cache->Access(access); |
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} |
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} |
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} |
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} // namespace rocksdb
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@ -0,0 +1,98 @@ |
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// Copyright (c) 2011-present, Facebook, Inc. All rights reserved.
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// This source code is licensed under both the GPLv2 (found in the
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// COPYING file in the root directory) and Apache 2.0 License
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// (found in the LICENSE.Apache file in the root directory).
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#pragma once |
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#include "rocksdb/utilities/sim_cache.h" |
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#include "trace_replay/block_cache_tracer.h" |
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namespace rocksdb { |
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const uint64_t kMicrosInSecond = 1000000; |
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// A cache configuration provided by user.
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struct CacheConfiguration { |
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std::string cache_name; // LRU.
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uint32_t num_shard_bits; |
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std::vector<uint64_t> |
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cache_capacities; // simulate cache capacities in bytes.
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bool operator=(const CacheConfiguration& o) const { |
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return cache_name == o.cache_name && num_shard_bits == o.num_shard_bits; |
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} |
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bool operator<(const CacheConfiguration& o) const { |
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return cache_name < o.cache_name || |
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(cache_name == o.cache_name && num_shard_bits < o.num_shard_bits); |
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} |
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}; |
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// A cache simulator that runs against a block cache trace.
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class CacheSimulator { |
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public: |
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CacheSimulator(std::shared_ptr<SimCache> sim_cache); |
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virtual ~CacheSimulator() = default; |
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// No copy and move.
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CacheSimulator(const CacheSimulator&) = delete; |
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CacheSimulator& operator=(const CacheSimulator&) = delete; |
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CacheSimulator(CacheSimulator&&) = delete; |
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CacheSimulator& operator=(CacheSimulator&&) = delete; |
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virtual void Access(const BlockCacheTraceRecord& access); |
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void reset_counter() { sim_cache_->reset_counter(); } |
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double miss_ratio(); |
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uint64_t total_accesses(); |
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protected: |
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std::shared_ptr<SimCache> sim_cache_; |
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}; |
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// A prioritized cache simulator that runs against a block cache trace.
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// It inserts missing index/filter/uncompression-dictionary blocks with high
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// priority in the cache.
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class PrioritizedCacheSimulator : public CacheSimulator { |
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public: |
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PrioritizedCacheSimulator(std::shared_ptr<SimCache> sim_cache) |
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: CacheSimulator(sim_cache) {} |
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void Access(const BlockCacheTraceRecord& access) override; |
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}; |
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// A block cache simulator that reports miss ratio curves given a set of cache
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// configurations.
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class BlockCacheTraceSimulator { |
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public: |
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// warmup_seconds: The number of seconds to warmup simulated caches. The
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// hit/miss counters are reset after the warmup completes.
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BlockCacheTraceSimulator( |
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uint64_t warmup_seconds, uint32_t downsample_ratio, |
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const std::vector<CacheConfiguration>& cache_configurations); |
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~BlockCacheTraceSimulator() = default; |
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// No copy and move.
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BlockCacheTraceSimulator(const BlockCacheTraceSimulator&) = delete; |
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BlockCacheTraceSimulator& operator=(const BlockCacheTraceSimulator&) = delete; |
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BlockCacheTraceSimulator(BlockCacheTraceSimulator&&) = delete; |
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BlockCacheTraceSimulator& operator=(BlockCacheTraceSimulator&&) = delete; |
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Status InitializeCaches(); |
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void Access(const BlockCacheTraceRecord& access); |
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const std::map<CacheConfiguration, |
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std::vector<std::shared_ptr<CacheSimulator>>>& |
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sim_caches() const { |
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return sim_caches_; |
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} |
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private: |
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const uint64_t warmup_seconds_; |
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const uint32_t downsample_ratio_; |
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const std::vector<CacheConfiguration> cache_configurations_; |
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bool warmup_complete_ = false; |
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std::map<CacheConfiguration, std::vector<std::shared_ptr<CacheSimulator>>> |
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sim_caches_; |
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uint64_t trace_start_time_ = 0; |
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}; |
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} // namespace rocksdb
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