Set CACHE_LINE_SIZE for s390, PPC, ARM64

Summary: Closes https://github.com/facebook/rocksdb/pull/2579 Differential Revision: D5427667 Pulled By: maysamyabandeh fbshipit-source-id: cd0b076aa0cd38d3554516f01723c548713ece61
8 years ago · ccf5f08f88
parent 67510eeff3
commit ccf5f08f88
1 changed files with 7 additions and 1 deletions
--- a/port/port_posix.h
+++ b/port/port_posix.h
@ -186,7 +186,13 @@ typedef pthread_once_t OnceType;
 extern void InitOnce(OnceType* once, void (*initializer)());

 #ifndef CACHE_LINE_SIZE
-#define CACHE_LINE_SIZE 64U
+  #if defined(__s390__)
+    #define CACHE_LINE_SIZE 256U
+  #elif defined(__powerpc__) || defined(__aarch64__)
+    #define CACHE_LINE_SIZE 128U
+  #else
+    #define CACHE_LINE_SIZE 64U
+  #endif
 #endif

 #define PREFETCH(addr, rw, locality) __builtin_prefetch(addr, rw, locality)