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Set CACHE_LINE_SIZE for s390, PPC, ARM64

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Summary: Closes https://github.com/facebook/rocksdb/pull/2579

Differential Revision: D5427667

Pulled By: maysamyabandeh

fbshipit-source-id: cd0b076aa0cd38d3554516f01723c548713ece61
main
Daniel Black 8 years ago committed by Facebook Github Bot
parent 67510eeff3
commit ccf5f08f88
1 changed files with 7 additions and 1 deletions
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  1. 8
      port/port_posix.h

8
port/port_posix.h
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@ -186,7 +186,13 @@ typedef pthread_once_t OnceType;
extern void InitOnce(OnceType* once, void (*initializer)()); extern void InitOnce(OnceType* once, void (*initializer)());
#ifndef CACHE_LINE_SIZE #ifndef CACHE_LINE_SIZE
#define CACHE_LINE_SIZE 64U #if defined(__s390__)
#define CACHE_LINE_SIZE 256U
#elif defined(__powerpc__) || defined(__aarch64__)
#define CACHE_LINE_SIZE 128U
#else
#define CACHE_LINE_SIZE 64U
#endif
#endif #endif
#define PREFETCH(addr, rw, locality) __builtin_prefetch(addr, rw, locality) #define PREFETCH(addr, rw, locality) __builtin_prefetch(addr, rw, locality)

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